Application Note: Quick Guide for Power Losses Calculation in MOSFETS

Approach to Estimate Switching Time Intervals Using Datasheet Parameters

In Part I of this application note series, a practical framework was introduced to estimate switching power losses in Power MOSFETs by calculating turn-ON and turn-OFF time intervals. These equations provide a useful first-order method for evaluating switching behavior in hard-switching applications using a simplified driver model.

However, applying these equations in real design scenarios quickly reveals a common challenge: several key parameters required for the calculations are strongly dependent on operating conditions and are not always directly available from datasheets in a form suitable for comparison.

This second part of the series addresses that gap.

1. Introduction

In Part I of this series, equations were developed to calculate MOSFET turn ON and turn OFF switching time intervals. These time intervals form the basis for switching power loss calculations in hard switching applications.

When applying these equations, it becomes evident that additional guidance is required. Several parameters used in the calculations, particularly gate plateau voltage and parasitic capacitances, depend strongly on operating voltage and current conditions. These parameters are not always directly available for the intended use case.

This application note provides practical methods to estimate these parameters using commonly available datasheet information. Approaches for plateau voltage approximation, reverse transfer capacitance extraction, and output capacitance modeling are presented. These methods enable consistent comparison of MOSFET switching behavior across suppliers when detailed SPICE models are not available.

The techniques described in this Part II are intended for component level comparison and early-stage device selection. When the objective is application-level loss modeling or worst-case analysis, time domain simulation using validated SPICE models remains the preferred approach.

1.1 ON and OFF time intervals

From Part I of this series, time intervals for the turn-ON transition are given as follows:

Formula 1

Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 2

Formula 2

3 Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 3

Formula 3

In addition, the turn-OFF transition time intervals were found to be:

Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 4

Formula 4

Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 5

Formula 5

Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 6

Formula 6

Where $𝜏 = R_{G} (C_{G S} + C_{G D})$ _{$𝜏 = R_{G} (C_{G S} + C_{G D})$} $𝜏 = R_{G} (C_{G S} + C_{G D})$ , the time intervals are defined as in Figure 1, and the following parameter definition apply:

$R_{G}$ : Gate resistance (internal and external).

$C_{GS}$ : Parasitic Gate-to-Source Capacitance.

$C_{GD}$ : Parasitic Gate-to-Drain Capacitance.

$R_{{DS}_{(on)}}$ : Drain-to-Source resistance when MOSFET is fully-ON.

$V_{th}$ : Threshold Voltage.

$V_{gp - ON}$ : Plateau Voltage during ON transition.

$V_{gp - OFF}$ : Plateau Voltage during OFF transition.

$V_{GG}$ : Gate external voltage supply DC value.

$V_{DD}$ Drain external voltage supply DC value.

$I_{o}$ : Drain load DC current.

Formulas 1-6 were derived from a Low-Side Driver sample circuit with inductive load and ideal recirculating diode as the one shown in Figure 2.

Figure 1a: Turn-On MOSFET Waveforms	Figure 1b: Turn-Off MOSFET Waveforms

Figure 1 – Switching Transition Waveforms

figure 6 LSD Circuit with inductive load MCC semi - micro commercial components 600x400

Figure 2 – Low-Side Driver Sample Circuit

2. Parameter approximations

2.1 Plateau Voltage for ON and OFF stages

It is clear from equations 2-4 and 6 that Gate Plateau Voltage is a parameter of high importance. However, deciding what voltage to use is often difficult.

Datasheet will show a Plateau Voltage under a determined set of conditions of Drain Voltage and Current. This value can be extracted from the datasheet Gate Charge plot to be used for calculations (Figure 3).

Figure 3 – Typical Gate Charge plot from Power MOSFET datasheet - MCC semi

Figure 3 – Typical Gate Charge plot from Power MOSFET datasheet

Nevertheless, conditions for measuring Plateau Voltage are not standard and therefore looking for an approximation that considers surrounding conditions makes sense.

According to [1] Plateau Voltage might even be different depending if the device is turning OFF or turning ON, and it will be defined by the following equations:

Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 7

Formula 7

8 Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 8

Formula 8

Where g_m is the transconductance obtained from the slope of the linear portion of the Transfer Characteristics (Figure 4).

Equations 7 and 8 are an option to derive Plateau Voltages for ON and OFF stages that bring datasheet Plateau to closer reference conditions for parameter comparison of two or more Power MOSFET Part-Numbers.

Figure 4 – Typical Transfer Characteristics Plot from Power MOSFET datasheet MCC semi

Figure 4 – Typical Transfer Characteristics Plot from Power MOSFET datasheet

2.2 Reverse Transfer Capacitance ( $𝑪_{𝒓 𝒔 𝒔}$ )

From Part I of this series, we know that Reverse Transfer Capacitance $C_{r s s}$ _{$C_{r s s}$ $C_{r s s}$ $C_{r s s}$} $C_{r s s}$ is equal to $C_{G D}$ which is a major parameter for equations 3 and 5. C_GD can be obtained by using Gate-Drain charge, $Q_{G D}$ , from datasheet dynamic characteristic tables, which lets the following formula to be applied:

Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 9

Formula 9

When using this method, it needs to be considered that $Q_{G D}$ is obtained with a determined V_GSvalue different from zero and that $C_{G D}$ non-linear capacitor is both dependent on $V_{G S}$ and $V_{D S}$ bias values (Figure 5)

Figure 5. Example of Gate-Drain Charge from Power MOSFET Datasheet mcc semi micro comercial components .

Figure 5. Example of Gate-Drain Charge from Power MOSFET Datasheet

Another way of approaching this capacitance will let us have values obtained from a standard method [3] that uses same measurement conditions making component comparison more trustable. $C_{r s s}$ characteristics plot, Figure 6, is obtained with a sweep of bias voltages for $V_{D S}$ with added small signal $v d s$ high frequency disturbances (i.e. capacitances in Figure 6 are small signal capacitances). It is worth noting that is an industry standard to have $V_{G S} = 0 V$ during this characterization.

Figure 6 – Example MOSFET Small-Signal Capacitance plots from Datasheet

From this plot, we can read the $C_{r s s} = C_{G D}$ value to desired $V_{D S}$ voltage and use it for time interval calculations. That is one valid way of doing it, sufficiently good for comparison purposes. Alternative way is to find an equivalent linear capacitor value related to the charge on the non-linear capacitor at the desired $V_{D S}$ . To do this, all points in the $C_{r s s}$ capacitance characteristics need to be extracted and used to simulate the non-linear charge curve with respect to its terminal voltages using the method in [2]. $C_{G D}$ is then obtained applying formula (9). These last two methods allow us to have $C_{G D}$ values for all MOSFETs in comparison that use the same $V_{D S}$ and $V_{G S}$ bias conditions.

This last simulation step can be regarded as an unnecessary extra step if the analysis goal is just to compare component performance. However, having this simulation allows detailing the non-linear capacitors more completely as is shown in Figure 7.

Figure 7 – Non-linear capacitor charge curve mcc semi

Figure 7 – Non-linear capacitor charge curve (C_d – small signal capacitance at V_x, C_t – equivalent linear capacitor at V_x)

2.3 Output Capacitance (𝑪𝒐𝒔𝒔)

Once $C_{G D}$ is defined, the same approach can be taken for $C_{D S}$ . In similarity with $C_{r s s}$ , Output Capacitance $C_{o s s}$ is defined in Figure 6 plot. Same benefit of having measurements with a well stablished method is accomplished, this makes conditions between suppliers similar and comparable.

The value of $C_{D S}$ is obtained after applying the following subtraction:

Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 10

Formula 10

Where, as was detailed above, $C_{o s s}$ can be read directly from the small signal non-linear capacitance plot (Figure 5) or the points from this characteristic can be extracted to simulate the non-linear charge curve with respect to Drain-to-Source voltage [2] and use:

Application Note Quick Guide for Power Losses Calculation in MOSFETS – Part 2 MCC semi 11

Formula 11

2.4 Gate-Threshold Voltage (V_th)

For this application note, the typical threshold voltage defined in the datasheet is used. No detailed calculation method was found in the literature.

In addition, manufacturers typically use the same measurement conditions, namely $V_{D S} = V_{G S}$ $I_{D} = 250 µ A$ , which makes comparison between devices more straightforward (Figure 8).

Figure 8. Typical Gate-Threshold Datasheet table MCC semi

Figure 8 - Typical Gate-Threshold Datasheet table

3. Calculation example

3.1 Sample circuit

Taking the following values for surrounding conditions on Figure 1 Low-Side driver circuit:

$V_{G G} = 10 V$ , $V_{D D} = 75 V$ , $I_{o} = 15 A$ , $R_{g_{e x t}} = 10 Ω$

an example calculation will be presented here.

For this MCC’s Power MOSFET MCAC15N15Y will be used along with two competitor MOSFETs that are close in electrical characteristics. Table 1 and Table 2 show these component parameters that are relevant for this analysis.

Parameter	Symbol	MCAC15N15Y	Conditions
Drain-Source Maximum Voltage	$V_{D S}$	150V	$V_{G S} = 0 V$ , $I_{D} = 250 𝜇 A$
Gate-Threshold Voltage	$V_{G S (t h)}$	2V to 4V	$V_{D S} = V_{G S}$ , I_D $I_{D} = 250 µ A$
Drain-Source On-Resistance	$r_{{D S}_{(o n)}}$	52mΩ (typ) 70mΩ (max)	$V_{G S} = 10 V$ , I_D $I_{D} = 15 A$
Internal Gate Resistance	$R_{g i n t}$	1Ω	$f = 1 M H z$ , Open drain
Gate-Drain Charge	$Q_{G D}$	4nC	$V_{D S} = 75 V$ , V_GS $V_{G S} = 10 V$ , I_D $I_{D} = 15 A$
Plateau-Voltage	$V_{p}$	4.9V	$V_{D S} = 75 V$ , I_D $I_{D} = 15 A$
Input Capacitance	$C_{i s s} = C_{G S} + C_{G D}$	749.9pF	$V_{D S} = 30 V$ , V_GS $V_{G S} = 0 V$ , f=1MH_z
Output Capacitance	$C_{o s s} = C_{D S} + C_{G D}$	301.1pF	$V_{D S} = 30 V$ , V_GS $V_{G S} = 0 V$ , f=1MH_z
Reverse Transfer Capacitance	${C_{r s s} = C}_{G D}$	27.3pF	$V_{D S} = 30 V$ , V_GS $V_{G S} = 0 V$ , f=1MH_z

Table 1. Electrical parameters for MCAC15N15Y relevant for calculations.

Symbol	Competitor A	Conditions	Competitor B	Conditions
$V_{D S}$	200V	$V_{G S} = 0 V$ , I_D $I_{D} = 250 𝜇 A$	150V	$V_{G S} = 0 V$ , I_D $I_{D} = 250 𝜇 A$
$V_{G S (t h)}$	2V to 4V	$V_{D S} = V_{G S}$ , I_D $I_{D} = 1 m A$	2V to 4V	$V_{D S} = V_{G S}$ , I_D $I_{D} = 35 µ A$
$r_{{D S}_{(o n)}}$	86mΩ (typ) 102mΩ (max)	$V_{G S} = 10 V$ , I_D $I_{D} = 12 A$	42mΩ (typ) 52mΩ (max)	$V_{G S} = 10 V$ , I_D $I_{D} = 18 A$
$R_{g i n t}$	1.1Ω	$f = 1 M H z$	2.1Ω	$f = 1 M H z$
$Q_{G D}$	10.1nC	$V_{D S} = 100 V$ , $V_{G S} = 10 V$ , I_D $I_{D} = 12 A$	1.5nC	$V_{D S} = 75 V$ , V_GS $V_{G S} = 10 V$ , I_D $I_{D} = 9 A$
$V_{p}$	4.5V	$V_{D S} = 100 V$ , I_D $I_{D} = 12 A$	5.2V	$V_{D S} = 75 V$ , I_D $I_{D} = 9 A$
$C_{i s s} = C_{G S} + C_{G D}$	1568pF	$V_{D S} = 30 V$ , V_GS $V_{G S} = 0 V$ $f = 1 M H z$	670pF	$V_{D S} = 75 V$ , V_GS $V_{G S} = 0 V$ , $f = 1 M H z$
$C_{o s s} = C_{D S} + C_{G D}$	170pF	$V_{D S} = 30 V$ , V_GS $V_{G S} = 0 V$ , $f = 1 M H z$	80pF	$V_{D S} = 75 V$ , V_GS $V_{G S} = 0 V$ , $f = 1 M H z$
${C_{r s s} = C}_{G D}$	55pF	$V_{D S} = 30 V$ , V_GS $V_{G S} = 0 V$ , $f = 1 M H z$	3.4pF	$V_{D S} = 75 V$ , V_GS $V_{G S} = 0 V$ , $f = 1 M H z$

Table 2. Electrical parameters for competition that are relevant for calculations.

3.2 LTspice Simulation of Sample Circuit

Simulations using SPICE models from MCAC15N15Y and Competition were performed. From simulation results measured time intervals $t_{O N} = t_{21_{O N}} + t_{32_{O N}}$ and $t_{O F F} = t_{21_{O F F}} + t_{32_{O F F}}$ are going to be used in this analysis as a reference. Results are shown in Table 3. Figure 9 shows $t_{O N}$ measurement from simulations taken from the point where the 5% of maximum Drain current is reached ( $0.05 * I_{o} = 0.75 A$ ) to the point where 5% of the maximum Drain voltage is reached ( $0.05 * V_{D D} = 3.75 V$ ). Same points, but with voltage appearing first than current were taken to measure $t_{O F F}$ (Figure 10).

	MCAC15N15Y	Competitor A	Competitor B	Δ (MCC – Competition)
	MCAC15N15Y	Competitor A	Competitor B	A	B
$t_{O N} = t_{21_{O N}} + t_{32_{O N}}$	8.68ns	18.40ns	5.46ns	-9.72ns	3.22ns
$t_{O F F} = t_{21_{O F F}} + t_{32_{O F F}}$	12.43ns	23.00ns	5.91ns	-10.57ns	6.52ns

Table 3. Turn-on and turn-off times obtained from simulation measurements

Figure 8. MCAC15N15Y Turn-on time from Simulation MCC semi

Figure 9. MCAC15N15Y Turn-on time from Simulation (

I_{o}

in green,

V_{D S}

in dark blue &

V_{G G}

in light blue)

Figure 9. MCAC15N15Y Turn-off time from Simulation MCC semi

Figure 10. MCAC15N15Y Turn-off time from Simulation (

I_{o}

in green,

V_{D S}

in dark blue &

V_{G G}

in light blue)

3.3 Calculation Using Datasheet Values

Calculations using datasheets values shown in Table 1 and Table 2 were used to calculate results in Table 4.

	MCAC15N15Y	Competitor A	Competitor B	Δ (MCC – Competition)
	MCAC15N15Y	Competitor A	Competitor B	A	B
$t_{10_{O N}}$	2.94ns	6.26ns	2.91ns	- -	- -
$t_{21_{O N}}$	2.61ns	4.24ns	3.08ns	- -	- -
$t_{32_{O N}}$	4.37ns	8.26ns	2.02ns	- -	- -
$t_{O N} = t_{21_{O N}} + t_{32_{O N}}$	6.98ns	12.49ns	5.1ns	-5.51ns	1.88ns
$t_{10_{O F F}}$	5.89ns	14.02ns	5.33ns	- -	- -
$t_{21_{O F F}}$	4.55ns	10.09ns	1.87ns	- -	- -
$t_{32_{O F F}}$	4.05ns	7.12ns	4.48ns	- -	- -
$t_{O F F} = t_{21_{O F F}} + t_{32_{O F F}}$	8.60ns	17.21ns	6.35ns	-8.61ns	2.25ns

Table 4. Calculation results using datasheet values.

3.4 Calculation Using Plateau Voltage

Modeling approach of Plateau Voltage described in Section 2.1 was used to obtain results shown in Table 5.

	MCAC15N15Y	Competitor A	Competitor B	Δ (MCC – Competition)
$t_{10_{O N}}$	2.94ns	6.33ns	2.91ns	- -	- -
$t_{21_{O N}}$	1.22ns	1.35ns	1.80ns	- -	- -
$t_{32_{O N}}$	3.69ns	7.00ns	1.73ns	- -	- -
$t_{O N} = t_{21_{O N}} + t_{32_{O N}}$	4.91ns	8.35ns	3.52ns	-3.44ns	1.39ns
$t_{10_{O F F}}$	8.60ns	18.78ns	8.99ns	- -	- -
$t_{21_{O F F}}$	6.32ns	13.23ns	2.92ns	- -	- -
$t_{32_{O F F}}$	1.33ns	2.36ns	0.82ns	- -	- -
$t_{O F F} = t_{21_{O F F}} + t_{32_{O F F}}$	7.65ns	15.59ns	3.75ns	-7.94ns	3.90ns

Table 5. Calculation results using Plateau Voltage model (Section 2.1)

4. Conclusions

Comparing the switching performance of Power MOSFETs across different manufacturers, or between part numbers from the same manufacturer, remains inherently challenging. Variations in measurement conditions directly influence reported device parameters and, as a result, affect any switching performance prediction.

This application note demonstrates that both direct use of datasheet values and the additional plateau voltage modeling approach provide reliable results for comparative analysis. Each method offers a practical approximation of relative switching speed, enabling meaningful comparison of how quickly one device transitions relative to another.

Delta-based comparisons derived from either approach give a clear indication of relative switching performance when devices are evaluated under equivalent operating conditions. The plateau voltage modeling approach presented in this work further improves consistency by normalizing comparisons to a common reference point, which is particularly valuable when published plateau voltage specifications are measured under differing test conditions.

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References:

[1] Liu, S., Song, S., Xie, N., Chen, H., Wu, X., & Zhao, M. (2021). Miller Plateau Corrected with Displacement Currents and Its Use in Analyzing the Switching Process and Switching Loss. Electronics 2021, 10
[2] Ben-Yaakov, S. & Zeltser, I. (2017). On SPICE simulation of voltage dependent capacitors. IEEE Transactions in Power Electronics
[3]JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (1985). JESD24 JEDEC Standard for Power MOSFETs

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Application Note: Quick Guide for Power Losses Calculation in MOSFETS – Part 2

Application Note: Quick Guide for Power Losses Calculation in MOSFETS – Part 2

Approach to Estimate Switching Time Intervals Using Datasheet Parameters

1. Introduction

1.1 ON and OFF time intervals

2. Parameter approximations

2.1 Plateau Voltage for ON and OFF stages

2.2 Reverse Transfer Capacitance ( $𝑪_{𝒓 𝒔 𝒔}$ )

2.3 Output Capacitance (𝑪𝒐𝒔𝒔)

2.4 Gate-Threshold Voltage (V_th)

3. Calculation example

3.1 Sample circuit

3.2 LTspice Simulation of Sample Circuit

3.3 Calculation Using Datasheet Values

3.4 Calculation Using Plateau Voltage

4. Conclusions

References:

Tags:

Application Note: Quick Guide for Power Losses Calculation in MOSFETS – Part 2

Application Note: Quick Guide for Power Losses Calculation in MOSFETS – Part 2

Approach to Estimate Switching Time Intervals Using Datasheet Parameters

1. Introduction

1.1 ON and OFF time intervals

2. Parameter approximations

2.1 Plateau Voltage for ON and OFF stages

2.2 Reverse Transfer Capacitance (𝑪𝒓𝒔𝒔)

2.3 Output Capacitance (𝑪𝒐𝒔𝒔)

2.4 Gate-Threshold Voltage (Vth)

3. Calculation example

3.1 Sample circuit

3.2 LTspice Simulation of Sample Circuit

3.3 Calculation Using Datasheet Values

3.4 Calculation Using Plateau Voltage

4. Conclusions

References:

Tags:

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2.2 Reverse Transfer Capacitance ( $𝑪_{𝒓 𝒔 𝒔}$ )

2.4 Gate-Threshold Voltage (V_th)