Design engineers face a growing challenge in optimizing power efficiency in modern electronic systems, especially as applications demand faster switching speeds and higher performance. Whether in automotive control units, industrial motor drives, or consumer electronics, excessive power dissipation during switching events can lead to increased thermal stress, reduced reliability, and higher energy costs.
One of the most critical contributors to power loss in these systems is switching loss in MOSFETs. This becomes particularly significant in circuits involving inductive loads. Despite the widespread use of MOSFETs for their fast-switching capabilities and ease of control, accurately estimating and comparing switching losses across different components remains a complex task.
Focus here is on calculating switching times, which are essential for understanding dynamic power dissipation. MCC offers a range of Power MOSFETs optimized for switching applications (see Table 1). One of these parts will be used as a reference in the calculation and simulation examples presented in the following sections of this series.
|
Part Number |
Package |
Type |
VDS (V) |
RDS(ON) |
Ciss(pF) |
Coss(pF) |
Crss(pF) |
Qg(nC) |
|
DFN5060 |
N |
40 |
0.0088 |
681 |
296 |
6.6 |
12 |
|
|
DFN3333 |
N |
30 |
0.0059 |
594 |
491 |
43 |
12.4 |
|
|
DFN5060 |
N |
30 |
0.0055 |
560 |
500 |
50 |
12.4 |
|
|
DFN5060 |
N |
100 |
0.033 |
509 |
271 |
35 |
12.7 |
|
|
DFN5060 |
N |
150 |
0.07 |
740 |
65 |
5 |
13 |
Table - 1. MCC Power MOSFET line-up for switching applications
The Power MOSFET is a voltage-controlled unipolar device that requires only a small amount of input (Gate, G) current (non-latching) to operate. The MOSFET will continue to allow current to flow between Drain (D) and Source (S) if the required amount of Gate (G) to Source (S) voltage, VGS, is maintained, as seen in Figure-1.
Figure-1. Power MOSFET terminal diagram
Since only majority carriers contribute to the current flow, MOSFETs have a high switching speed capability (exceeding several hundreds of kHz in practical applications).
For MOSFETs to carry Drain current, a channel between the Drain and the Source must be created. This occurs when the Gate-to-Source exceeds the device threshold voltage (Vth) For vGS > Vth the device can be either in the triode region (constant resistance) or in the saturation region depending on the Drain to Source vDS value as shown in Figure-2.
Figure-2. Working regions of the MOSFET based on the iD vs vDS characteristic.
When the MOSFET is used as a switch, only triode and cut-off regions are used, whereas, when it is used as a controlled-current source, the MOSFET must operate in the saturation region.
Parasitic Capacitances are important parameters that affect the MOSFET’s switching behavior. They are located between the device’s 3 terminals, namely: Gate-to-Source (CGS), Gate-to-Drain (CGD), and Drain-to-Source (CDS) capacitances, see Figure-3.
Figure-3. MOSFET parasitic capacitances.
The values of these capacitances are non-linear and a function of device structure, geometry and, particularly, of bias voltages. The MOSFET parasitic capacitances are given in terms of the typical device datasheet parameters (Figure-4) that are easier to measure Ciss, Coss and Crss. The relation is shown in Figure-3 bottom equations.
Figure-4. Typical Capacitance plots of a MOSFET Datasheet.
The turn-On and turn-Off processes of semiconductor devices are not discrete events; there will be a delay time between iDS = IDS_MAX (On state) and iDS ≈ 0 (Off state). According to previous authors, these times can be divided into 3 different intervals of time, as can also be seen in the figures for turn-On and turn-Off events: Figure-5.a and Figure-5.b, respectively. In this document we will find a way of calculating:
Figure-5. a) Turn-On MOSFET waveforms Figure -5.b) Turn-Off MOSFET waveforms.
In this Application Note, we will explore a basic LSD power electronic circuit operating under an inductive load. We will assume that the load inductance (L0) is large enough to consider the current through it as constant with value Io (modeled with a current source in Figure-6). Also, a lossless flyback diode D (see Figure-6) used to pick up the load current during the MOSFET OFF-state is included.
Figure-6. LSD circuit with inductive load.
First, let’s assume the device is off, the load current I0 flows through D and vGS = VGG = 0. The voltage vDS = VDD and iG = iD = 0. At t=t0, the voltage VGG is applied (Figure-5.a). The sudden voltage in VGG starts moving charge from CGS and CGD through RG.
Figure-7. MOSFET during t10ON with vGS < Vth and iD = 0.
During t0 ≤ < t1 (t10ON), vGS < Vth having the MOSFET in the cut-off region with iD = 0 regardless of vDS value.
This interval represents the delay turn-on time needed to bring voltages at CGS and CGD from zero to Vth and from VDD to VDD−Vth, respectively. The expression for the t10ON can be obtained considering that the Gate current is given by:
Given that during t10ON the only voltage changing with time is vGS (vDS = VDD, constant) we can rewrite the equation as follows:
On the other side, iG =(VGG−vGS)/RG, so the equation can be expressed as:
Therefore, solving the differential equation for vGS, t > t0 and vGS(t0) = 0 we obtain:
For t1 ≤ t < t2 (t21ON) the condition vGS > Vth is true causing the MOSFET to start conducting having iD ≠ 0. This initial stage of the turn-On current is given by the transconductance equation:
Figure-8. Input transfer characteristics for small changes
As long as vGS < Vplateau, the equation for vGS remains the same as in t10ON, so:
Figure-9. MOSFET during t21tON with vGS > Vth and iD < I0
Reaching t = t2, iD arrives at its maximum value of I0. Considering iD(t2) = I0, the time interval t2 − t0 can be solved from iD(t) equation previously found, resulting:
From Figure-5.a, when t = t2, vGS is also constant and equal to its On-State Plateau Voltage Vgp−ON (S. Liu, et all.), then we can write:
allowing to simplify:
Finally, t21ON can be obtained using t10ON found previously:
For t2 ≤ t < t3 (t32ON), iD = I0 and CDS discharges from vDS = VDD to vDS = I0RDSon, where RDSon is the On-state resistance of the MOSFET. Since vGS during t32ON is constant, the entire gate current flows through CGD:
and:
considering vGS=Vgp−ON ,vDS(t2) = VDD and the interval Δt=t32ON:
The time interval t32ON is determined by assuming that at t = t3 the drain-to-source voltage reaches its minimum value determined by its on resistance:
Figure-10. MOSFET during t32ON with vGS > Vth , iD=I0
Then, the time t32ON is obtained:
A similar analysis as the one performed in the previous section can be done for the Turn-Off transition timings. For reason of space, only the results are shown below, but procedure is available upon request.
Time it takes vGS to go from its maximum value to the plateau value Vgp−OFF.
Time it takes vDS to go from its ON-state voltage back to VDS_MAX, in this case I0rDS(on) and VDD, respectively:
Time it takes drain current to go from IDS_MAX back to zero:
This Application Note introduced the methodology for calculating switching times, turn-on and turn-off transitions, of Power MOSFETs in low-side driver configurations with inductive loads. These calculations form the foundation for estimating switching losses and comparing device performance.
Upcoming notes in this series will build on this foundation, guiding engineers through the process of extracting key datasheet parameters, performing complete power consumption calculations, and applying the methodology to real MCC MOSFET part numbers. Each note is designed to provide practical insights and tools for making informed component selections in power-sensitive designs.
By using a consistent application example throughout, an LSD circuit with an inductive load, this series aims to simplify the comparison of switching losses across different MOSFETs, whether from multiple vendors or within a single product line.